CPUID

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CPUID

From Wikipedia, the free encyclopedia

The CPUID is a (its name derived from IDentification) for the architecture. It was introduced by in 1993 when it introduced the and processors.

By using the CPUID opcode, software can determine processor type and the presence of features (like /). The CPUID opcode is 0Fh, 0A2h (as two bytes, or 0A20Fh as a single word) and the value in the EAX register, and in some cases the ECX register, specifies what information to return.

Prior to the general availability of the CPUID instruction, programmers would write esoteric which exploited minor differences in CPU behavior in order to determine the processor make and model. Outside the x86 family, developers are sometimes still required to use esoteric processes to determine the variations in CPU design that are present. While the CPUID instruction is specific to the x86 architecture, other architectures often provide on-chip registers which can be read to obtain the same sorts of information provided by this instruction.

[]

Calling CPUID[]

In the CPUID instruction takes no parameters as CPUID implicitly uses the EAX register. The EAX register should be loaded with a value specifying what information to return. CPUID should be called with EAX = 0 first, as this will return the highest calling parameter that the CPU supports. To obtain extended function information CPUID should be called with the second most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID with EAX = 80000000h.

EAX=0: Get vendor ID[]

This returns the CPU's manufacturer ID string - a twelve character string stored in EBX, EDX, ECX - in that order. The highest basic calling parameter (largest value that EAX can be set to before calling CPUID) is returned in EAX.

The following are known processor manufacturer ID strings:

"AMDisbetter!" — early engineering samples of processor

"AuthenticAMD" —

"CentaurHauls" —

"CyrixInstead" —

"GenuineIntel" —

"TransmetaCPU" —

"GenuineTMx86" —

"Geode by NSC" —

"NexGenDriven" —

"RiseRiseRise" —

"SiS SiS SiS " —

"UMC UMC UMC " —

"VIA VIA VIA " —

"Vortex86 SoC" —

"KVMKVMKVMKVM" —

For instance, on a GenuineIntel processor values returned in EBX is 0x756e6547, EDX is 0x49656e69 and ECX is 0x6c65746e. The following code is written in for the architecture and displays the vendor ID string as well as the highest calling parameter that the CPU supports.

.data s0:        .asciz  "Largest basic function number supported: %i\n"s1:        .asciz  "Vendor ID: %.12s\n"         .text         .align  32        .globl  _start_start:        pushq   %rbp        pushq   %rbx        movq    %rsp,%rbp        subq    $16,%rsp         xorl    %eax,%eax        cpuid         movl    %ebx,0(%rsp)        movl    %edx,4(%rsp)        movl    %ecx,8(%rsp)         movq    $s0,%rdi        movl    %eax,%esi        xorb    %al,%al        call    printf         movq    $s1,%rdi        movq    %rsp,%rsi        xorb    %al,%al        call    printf         movq    %rbp,%rsp        popq    %rbx        popq    %rbp        movl    $1,%eax        int     $0x80

EAX=1: Processor Info and Feature Bits[]

This returns the CPU's , model, and family information in EAX (also called the signature of a CPU), feature flags in EDX and ECX, and additional feature info in EBX.

The format of the information in EAX is as follows:

3:0 - Stepping

7:4 - Model

11:8 - Family

13:12 - Processor Type

19:16 - Extended Model

27:20 - Extended Family

has suggested applications to display the family of a CPU as the sum of the "Family" and the "Extended Family" fields shown above, and the model as the sum of the "Model" and the 4-bit left-shifted "Extended Model" fields.

recommends the same only if "Family" is equal to 15 (i.e. all bits set to 1). If "Family" is lower than 15, only the "Family" and "Model" fields should be used while the "Extended Family" and "Extended Model" bits are reserved. If "Family" is set to 15, then "Extended Family" and the 4-bit left-shifted "Extended Model" should be added to the respective base values.

The processor info and feature flags are manufacturer specific but usually the Intel values are used by other manufacturers for the sake of compatibility.

The standard Intel feature flags are as follows

EAX=1 CPUID feature bits
Bit	EDX		ECX
Bit	Short	Feature	Short	Feature
0	fpu	Onboard FPU	pni	(SSE3)
1	vme	Virtual mode extensions (VIF)	pclmulqdq	support
2	de	Debugging extensions ( bit 3)	dtes64	64-bit debug store (edx bit 21)
3	pse		monitor	MONITOR and MWAIT instructions ()
4	tsc		ds_cpl	CPL qualified debug store
5	msr		vmx
6	pae		smx	Safer Mode Extensions ()
7	mce		est	Enhanced
8	cx8	CMPXCHG8 () instruction	tm2
9	apic	Onboard	ssse3	instructions
10	(reserved)		cid	Context ID
11	sep	SYSENTER and SYSEXIT instructions	(reserved)
12	mtrr		fma	(FMA3)
13	pge	Page Global Enable bit in	cx16	CMPXCHG16B instruction
14	mca		xtpr	Can disable sending task priority messages
15	cmov	Conditional move and instructions	pdcm	Perfmon & debug capability
16	pat		(reserved)
17	pse36		pcid	Process context identifiers ( bit 17)
18	pn		dca	Direct cache access for DMA writes
19	clflush	CLFLUSH instruction ()	sse4_1	instructions
20	(reserved)		sse4_2	instructions
21	dts	Debug store: save trace of executed jumps	x2apic	support
22	acpi	Onboard thermal control MSRs for	movbe	MOVBE instruction (, only)
23	mmx	instructions	popcnt	instruction
24	fxsr	FXSAVE, FXRESTOR instructions, bit 9	tscdeadline	APIC supports one-shot operation using a TSC deadline value
25	sse	instructions (a.k.a. Katmai New Instructions)	aes
26	sse2	instructions	xsave	XSAVE, XRESTOR, XSETBV, XGETBV
27	ss	CPU cache supports self-	osxsave	XSAVE enabled by OS
28	ht		avx
29	tm	Thermal monitor automatically limits temperature	f16c	() FP support
30	ia64	processor emulating x86	rdrnd	(on-chip random number generator) support
31	pbe	Pending Break Enable (PBE# pin) wakeup support	hypervisor	Running on a (always 0 on a real CPU, but also with some hypervisors)

EAX=2: Cache and TLB Descriptor information[]

This returns a list of descriptors indicating cache and capabilities in EAX, EBX, ECX and EDX registers.

EAX=3: Processor Serial Number[]

EAX=80000000h: Get Highest Extended Function Supported[]

The highest calling parameter is returned in EAX.

EAX=80000001h: Extended Processor Info and Feature Bits[]

This returns extended feature flags in EDX and ECX.

AMD feature flags are as follows

EAX=80000001h CPUID feature bits
Bit	EDX		ECX
Bit	Short	Feature	Short	Feature
0	fpu	Onboard FPU	lahf_lm	LAHF/SAHF in long mode
1	vme	Virtual mode extensions (VIF)	cmp_legacy	not valid
2	de	Debugging extensions ( bit 3)	svm
3	pse		extapic	Extended space
4	tsc		cr8_legacy	in 32-bit mode
5	msr		abm	Advanced bit manipulation ( and )
6	pae		sse4a
7	mce		misalignsse	Misaligned mode
8	cx8	CMPXCHG8 () instruction	3dnowprefetch	PREFETCH and PREFETCHW instructions
9	apic	Onboard	osvw	OS Visible Workaround
10	(reserved)		ibs
11	syscall	SYSCALL and SYSRET instructions	xop
12	mtrr		skinit	SKINIT/STGI instructions
13	pge	Page Global Enable bit in	wdt
14	mca		(reserved)
15	cmov	Conditional move and instructions	lwp	Light Weight Profiling
16	pat		fma4
17	pse36		tce	Translation Cache Extension
18	(reserved)
19	mp	Capable	nodeid_msr	NodeID MSR
20	nx		(reserved)
21	(reserved)		tbm	Trailing Bit Manipulation
22	mmxext		topoext	Topology Extensions
23	mmx	instructions	perfctr_core	Core performance counter extensions
24	fxsr	FXSAVE, FXRSTOR instructions, bit 9	perfctr_nb	NB performance counter extensions
25	fxsr_opt	FXSAVE/FXRSTOR optimizations	(reserved)
26	pdpe1gb	pages	(reserved)
27	rdtscp	RDTSCP instruction	(reserved)
28	(reserved)
29	lm		(reserved)
30	3dnowext		(reserved)
31	3dnow		(reserved)

EAX=80000002h,80000003h,80000004h: Processor Brand String[]

These return the processor brand string in EAX, EBX, ECX and EDX. CPUID must be issued with each parameter in sequence to get the entire 48-byte null-terminated ASCII processor brand string. It is necessary to check whether the feature is supported by the CPU by issuing CPUID with EAX = 80000000h first and checking if the returned value is greater or equal to 80000004h.

.section .data s0 : .asciz "Processor Brand String: %.48s\n"err : .asciz "Feature unsupported.\n" .section .text .global main.type main,@function.align 32main:        pushq   %rbp        movq    %rsp,   %rbp        subq    $48,    %rsp        pushq   %rbx         movl    $0x80000000,    %eax        cpuid         cmpl    $0x80000004,    %eax        jl      error         movl    $0x80000002,    %esi        movq    %rsp,   %rdi .align 16get_brand:        movl    %esi,   %eax        cpuid         movl    %eax,   (%rdi)        movl    %ebx,   4(%rdi)        movl    %ecx,   8(%rdi)        movl    %edx,   12(%rdi)         addl    $1,     %esi        addq    $16,    %rdi        cmpl    $0x80000004,    %esi        jle     get_brand print_brand:        movq    $s0,    %rdi        movq    %rsp,   %rsi        xorb    %al,    %al        call    printf         jmp     end .align 16error:        movq    $err,   %rdi        xorb    %al,    %al        call    printf .align 16end:        popq    %rbx        movq    %rbp,   %rsp        popq    %rbp        xorl    %eax,   %eax        ret

EAX=80000005h: L1 Cache and TLB Identifiers[]

This function contains the processor’s L1 cache and TLB characteristics.

EAX=80000006h: Extended L2 Cache Features[]

Returns details of the L2 cache in ECX, including the line size in bytes, type of associativity (encoded by a 4 bits) and the cache size.

.section .data info : .ascii "L2 Cache Size : %u KB\nLine size : %u bytes\n".asciz "Associativity : %02xh\n"err : .asciz "Feature unsupported.\n" .section .text .global main.type main,@function.align 32main:        pushq   %rbp        movq    %rsp,   %rbp        pushq   %rbx         movl    $0x80000000,    %eax        cpuid         cmpl    $0x80000006,    %eax        jl      error         movl    $0x80000006,    %eax        cpuid         movl    %ecx,   %eax         movl    %eax,   %edx        andl    $0xff,  %edx         movl    %eax,   %ecx        shrl    $12,    %ecx        andl    $0xf,   %ecx         movl    %eax,   %esi        shrl    $16,    %esi        andl    $0xffff,%esi         movq    $info,  %rdi        xorb    %al,    %al        call    printf         jmp end .align 16error:        movq    $err,   %rdi        xorb    %al,    %al        call    printf .align 16end:        popq    %rbx        movq    %rbp,   %rsp        popq    %rbp        xorl    %eax,   %eax        ret

EAX=80000007h: Advanced Power Management Information[]

This function provides advanced power management feature identifiers.

EAX=80000008h: Virtual and Physical address Sizes[]

Returns largest virtual and physical address sizes in EAX.

Accessing the id from other languages[]

This information is easy to access from other languages as well. For instance, the C++ code for gcc below prints the first five values, returned by the cpuid:

#include 
        
          int main(){
         int a, b;   for (a = 0; a < 5; a++)  {
           __asm__("cpuid;"            :"=a"(b)                 // EAX into b (output)            :"0"(a)                  // a into EAX (input)            :"%ebx","%ecx","%edx");  // clobbered registers     std::cout << "The code " << a << " gives " << b << std::endl;  }   return 0;}

In C, the code may be shortened to:

int main(){
         int a, b;   for (a = 0; a < 5; a++)  {
           __asm__("cpuid"            :"=a"(b)                 // EAX into b (output)            :"0"(a)                  // a into EAX (input)            :"%ebx","%ecx","%edx");  // clobbered registers     printf("The code %i gives %i\n", a, b);  }   return 0;}

Or, a generally useful C implementation that works on 32 and 64 bit setups:

#include 
        
          int main() {
           int i;    unsigned int index = 0;    unsigned int regs[4];    int sum;    __asm__ __volatile__(#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)        "pushq %%rbx     \n\t" /* save %rbx */#else        "pushl %%ebx     \n\t" /* save %ebx */#endif        "cpuid            \n\t"        "movl %%ebx ,%[ebx]  \n\t" /* write the result into output var */#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)        "popq %%rbx \n\t"#else        "popl %%ebx \n\t"#endif        : "=a"(regs[0]), [ebx] "=r"(regs[1]), "=c"(regs[2]), "=d"(regs[3])        : "a"(index));    for (i=4; i<8; i++) {
               printf("%c" ,((char *)regs)[i]);    }    for (i=12; i<16; i++) {
               printf("%c" ,((char *)regs)[i]);    }    for (i=8; i<12; i++) {
               printf("%c" ,((char *)regs)[i]);    }    printf("\n");}

Another version of that:

#include 
        
          void cpuid(unsigned info, unsigned *eax, unsigned *ebx, unsigned *ecx, unsigned *edx){
           __asm__(        "xchg %%ebx, %%edi;" /* 32bit PIC: don't clobber ebx */        "cpuid;"        "xchg %%ebx, %%edi;"        :"=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx)        :"0" (info)    );} int main(){
         unsigned int eax, ebx, ecx, edx;  int i;   for (i = 0; i < 6; ++i)  {
           cpuid(i, &eax, &ebx, &ecx, &edx);    printf("eax=%i: %#010x %#010x %#010x %#010x\n", i, eax, ebx, ecx, edx);  }   return 0;}

Microsoft Visual C compiler has builtin function __cpuid() so cpuid instruction may be embedded without using inline assembly. This is handy since x64 version of MSVC doesn't allow inline assembly at all. The same program for would be:

#include 
        
         #include 
         
           int main(){
         int b[4];   for (int a = 0; a < 5; a++)  {
           __cpuid(b, a);    std::cout << "The code " << a << " gives " << b[0] << std::endl;  }   return 0;}

For Borland/Embarcadero C compilers (bcc32), native asm function calls are necessary, as there is no asm() implementation. The pseudo code:

unsigned int a, b, c, d;  unsigned int InfoType = 0;  __asm xor EBX, EBX;  __asm xor ECX, ECX;  __asm xor EDX, EDX;  __asm mov EAX, InfoType;  __asm cpuid;  __asm mov a, EAX;  __asm mov b, EBX;  __asm mov c, ECX;  __asm mov d, EDX;

Many interpreted or compiled scripting languages are capable of using CPUID via an library. shows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode.

Uptake of CPUID instructions outside x86[]

The Intel-AMD x86 family has so far been the only CPU family to have a CPUID instruction. , and like chip families have not taken up the instruction in any noticeable way, in spite of having (in relative terms) as many variations in design. have a CPUID coprocessor register for the same purpose. IBM mainframe processor z10 and predecessors have had the Store CPUID (STIDP) instruction for querying the processor ID.

References[]

. Intel.com. Retrieved 2013-04-11.

. Rcollins.org. Retrieved 2013-04-11.

. Lxr.linux.no. Retrieved 2013-04-11.

^ . Download.intel.com. 2012-03-06. Retrieved 2013-04-11.

, , January 2011, retrieved 2011-05-29

Linux kernel source code

Huggahalli, Ram; Iyer, Ravi; Tetrick, Scott (2005). "Direct Cache Access for High Bandwidth Network I/O". 33 (2): 50–59.:.:.

Drepper, Ulrich (2007), What Every Programmer Should Know About Memory, :

, , September 2010, retrieved 2013-04-02

Linux kernel source code

, , August 2010, retrieved 2013-04-03

. Infocenter.arm.com. Retrieved 2013-04-11.

External links[]

CPUID guide (PDF)

CPUID guide (PDF)

CPUID utility for multi-processor platform

Intel Architecture and Processor Identification With CPUID Model and Family Numbers

Submitted by on Fri, 06/15/2012 - 08:27

This article is intended to aid software developers in understanding the "big picture" of Intel's recent architecture and processor releases. The adds predictability to the . However within each "tick" and "tock" architecture, multiple processors are launched to support the many diverse computing needs of consumers. While the general and feature set within a given architecture are identical, certain model specific variations occur, and are generally enumerated through CPUID interrogation. The CPUID model number is a convenient way of anticipating the model specific functionality that is available at runtime and subsequently designing the architecture specific parts of software (nevertheless, at runtime, the feature bits in the CPUID should always be verified before use).

The information in the table below is composed from the and the .

For identifying a particular processor, please use the for Microsoft Windows* operating systems or the for other operating systems.

Notes

The -EP suffix denotes a Dual Processor, meaning this processor is designed to operate in a Dual Processor platform (but can still operate in a Single Processor platform). The -EX suffix denotes a Multi-Processor (MP), meaning this processor is designed to operate in a Multiprocessor platform, but can still operate in a Single or Dual processor platform configuration.

The Family number is an 8-bit number derived from the processor signature by adding the Extended Family number (bits 27:20) and the Family number (bits 11:8). See section 5.1.2.2 of the .

The Model number is an 8 bit number derived from the processor signature by shifting the Extended Model number (bits 19:16) 4 bits to the left and adding the Model number (bits 7:4) . See section 5.1.2.2 of the .

This table includes the mainline processors on 90nm and later process technology. Please read and understand these important prior to use.

Process Technology	Microarchitecture Codename	Processor Codename	Processor Signature	Family Number	Model Number	Intel® Brand Name(s)	Intel® Brand Processor Number
22 nm	IvyBridge	IvyBridge	0x306Ax	0x06	0x3A	Core™ i3 Core™ i5 Core™ i7 Core™ i7 Extreme Xeon™ E3	i3-31xx/32xx-T/U i5-3xxx-T/S/M/K/ME i7-3xxx-S/K/M/QM/LE/UE/QE i7-3920XM E3-12xxV2
32 nm	SandyBridge	SandyBridge	0x206Ax		0x2A	Core™ i3 Core™ i5 Core™ i7 Core™ i7 Extreme Celeron™ Desktop Celeron™ Mobile Pentium™ Desktop Pentium™ Mobile Xeon™ E3	i3-21xx/23xx-T/M/E/UE i5-23xx/24xx/25xx-T/S/M/K i7-2xxx-S/K/M/QM/LE/UE/QE i7-29xxXM G4xx, G5xx 8xx, B8xx 350, G6xx, G6xxT, G8xx 9xx, B9xx E3-12xx
		SandyBridge-E	0x206Dx		0x2D	Core™ i7 Core™ i7 Extreme	I7-3820/3930K i7-3960X
		SandyBridge-EN				Xeon™ E5	E5-24xx
		SandyBridge-EP				Xeon™ E5	E5-16xx, 26xx/L/W
	Westmere	Arrandale	0x2065x		0x25	Celeron™ Mobile Pentium™ Mobile Core™ i3 Core™ i5 Core™ i7	P4xxx, U3xxx P6xxx, U5xxx i3-3xxE, i3-3xxM, i3-3xxUM i5-4xxM/UM, i5-5xxE/M/UM i7-6xxE/LE/UE/M/LM/UM
		Clarksdale	0x2065x		0x25	Pentium™ Desktop Core™ i3 Core™ i5 Xeon™ 3000	G69xx i3-5xx i5-6xx, i5-6xxK L34xx
		Gulftown	0x206Cx		0x2C	Core™ i7 Core™ i7 Extreme Xeon™ 3000	i7-9xx i7-9xxX W36xx
		Westmere-EP	0x206Cx		0x2C	Xeon™ 3000 Xeon™ 5000	W36xx L56xx, E56xx, X56xx
		Westmere-EX	0x206Fx		0x2F	Xeon™ E7	E7-2xxx, E7-48xx, E7-88xx
45 nm	Nehalem	Clarksfield	0x106Ex		0x1E	Core™ i7 Core™ i7 Extreme	i7-7xxQM, i7-8xxQM i7-9xxXM
		Lynnfield				Core™ i5 Core™ i7 Xeon™ 3000	i5-7xx, i5-7xxS i7-8xx, i7-8xxS, i7-8xxK X34xx
		Jasper Forest				Xeon™ 5000 Celeron™ Desktop	LC55xx, EC55xx P10xx
		Bloomfield	0x106Ax		0x1A	Core™ i7 Extreme Core™ i7 Xeon™ 3000	i7-965/975 i7-9x0 W35xx
		Nehalem-EP	0x106Ax		0x1A	Xeon™ 5000	L55xx, E55xx, X55xx, W55xx
		Nehalem-EX	0x206Ex		0x2E	Xeon™ 7000 Xeon™ 6000	L75xx, E75xx, X75xx E65xx, X65xx
	Penryn	Yorkfield	0x1067x		0x17	Core™ 2 Quad Core™ 2 Extreme Xeon™ 3000	Q9xxx, Q8xxx, !9xxxS QX9xxx L33xx, X3350
		Wolfdale				Celeron™ Desktop Core™ 2 Duo Pentium™ Xeon™ 5000/3000	E3xxx E7xxx, E8xxx E5xxx, E6xxx, E6xxxK L52xx, E31xx
		Penryn				Core™ 2 Duo Mobile Celeron™ M	P7xxx, P9xxx, SL9xxx 722
		Harpertown (DP)				Xeon™ 5000	L54xx, E54xx, X54xx
		Dunnington (MP)	0x106Dx		0x1D	Xeon™ 7000	L74xx, E74xx, Q7xx
65 nm	Merom	Clovertown	0x006Fx		0x0F	Xeon™ 5000	E53xx, L53xx, X53xx
		Kentsfield				Xeon™ 3000 Core™ 2 Quad Core™ 2 Extreme	X32xx Q6600 QX6xxx
		Conroe				Xeon™ 3000 Pentium™ Core™ 2 Duo Core™ 2 Extreme Celeron™ Desktop	30xx E21xx E43xx,E6xxx X6800 E1600
		Merom				Core™ 2 Duo M Pentium™ Mobile Core™ 2 Extreme M	L7xxx,T5xxx,T7xxx,U7xxx T3200 X7xxx
		Woodcrest				Xeon™ 5000	51xx
		Merom Conroe	0x1066x		0x16	Celeron™ Desktop Celeron™ Mobile	4xx 5xx
	Presler	Cedar Mill	0x0066x	0x0F	0x06	Pentium™ 4	3xx, 6xx
	Presler	Presler	0x0066x		0x06	Pentium™ D	9xx
90 nm	Prescott	Nocona Irwindale	0x0063x 0x0064x		0x03/ 0x04	Xeon™
	Prescott	Prescott	0x0063x 0x0064x		0x03/ 0x04	Celeron™ D Pentium™ 4	3xx 5xx
	Dothan	Dothan	0x006Dx	0x06	0x0D	Celeron™ M Pentium™ Mobile	3xx 7xx

This table includes the Atom™ processors on 45nm and later process technology. Please read and understand these important prior to use.

Process Technology	Microarchitecture Codename	Processor Codename	Platform Codename	Processor Signature	Family Number	Model Number	Intel® Brand Name(s)	Intel® Brand Processor Number
32 nm	Atom™	Cedarview	Cedar Trail	0x0366x	0x06	0x36	Atom™	N2000 series: N26xx, N28xx D2000 Series: D25xx (no HT), D27xx
45 nm		Lincroft	Oak Trail	0x0266x		0x26		Z6xx (single core)
		Pineview	Pine Trail	0x016Cx		0x1C		N4xx, D4xx (single core) N5xx, D5xx (dual core)
		Silverthorne	any	0x016Cx		0x1C		Z5xx

Information in this article is intended as a convenient summary of the contents of the application note and the .

In case of discrepancy, the information in the and supersede the contents of this article. (Please notify the author of any such discrepancy).

Please consult Section 2: Usage Guidelines of the for the proper use of CPUID.

Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See for details.

All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

For an example of interrogating CPUID to verify features please read

In Linux*-based operating systems you can type ‘cat /proc/cpuinfo' to obtain the processor family and model numbers (note they are formatted in decimal, while the tables in this article containhexadecimal formatting of these numbers).

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